Digital signal detectors of the prior art have utilized various techniques which make use of the fact that bit transitions occur in a predictable timing relationship with respect to one another. For example, in U.S. Pat. No. 3,939,431, there is described a detector which generates a window pulse at a predetermined time interval from the preceding bit transition, which time interval is one of two times depending on whether the preceding bit transition was a high to low, or low to high logical state change. If bit transitions occur during the window pulse, the detector provides an indication that the digital signal is present.
Another digital signal detector is described in U.S. Pat. No. 3,995,225, where a quadrature detector is combined with minimum and maximum bit width detectors. When the digital signal is present, bit transitions do not occur in quadrature with the recovered clock signal. Therefore, if bit transitions are detected in quadrature with the clock signal, noise and not the digital signal is present. Furthermore, if bit transitions are too close together or too far apart, noise is likewise determined to be present. However, neither of the foregoing detectors provides for variability of the detector threshold such that the sensitivity of the detector may be tailored to a particular communication channel. Moreover, neither of the prior art detectors provide hysteresis in the detector threshold, such that the threshold may be reduced subsequent to an initial detection of the digital signal. In addition, neither of the foregoing detectors can be rendered substantially immune to periodic signals having frequencies that are submultiples of the bit frequency of the digital signal.